Advanced System Design using HDLs
Catalog Listing "Introduction to VHDL"(ECGR 4146/5146 )
Spring 2011
A Design Flow is similar to a Cascading Waterfall
Lecture Timings 12:30pm – 1:45pm Tuesday, Thursday Room: Woodward 140
TA for class : None
TA office : None
TA office hours : None
Instructor office hours : Tuesdays, Thursdays 11:30pm – 12:30 pm @ Woodward 235B
Instructor Dr. Arindam Mukherjee
Course Description
This course is designed for junior/senior undergraduate students with a background in digital logic design and VHDL. The class meets twice a week with alternating lectures and laboratories. The lectures and laboratory sessions seeks to impart students the ability for FPGA based reconfigurable hardware implementation of computationally intensive algorithms from diverse areas such as bioinformatics, scientific computing and image processing. No background knowledge of these topics is required. Students are required to complete a design project involving implementation of a real world computational application on FPGAs. CAD tools including Xilinx ISE design flow and Modelsim are used extensively throughout the course.
Course Objectives
Ability to describe digital logic in VHDL.
Familiarity with FPGA design flow including interfacing issues.
Exposure to computing algorithms from diverse application areas.
Ability to map computationally intensive algorithms to FPGAs.
Successful project execution and presentation of results working in a team.
Prerequisites
ECGR 3181 Advanced Digital Logic Systems.
Textbook
Peter J. Ashenden, THE DESIGNER’S GUIDE TO VHDL, Third Edition, Elsevier Publishers, 2008.
Grading
Midterm ? 20%, Class Projects – 20%, Final ? 30%, Final Project and Presentation ? 30%
Course Topics (Subject to change)
- Review ofFiniteStateMachines
- Overview of VHDL ? Structure and Syntax
- Overview of VHDL ? Modeling
- Overview of VHDL – Synthesis
- FPGA Design Flow
- Interfacing FPGA based hardware accelerators to computers
- Design Case Studies
- Projects
Lecture Notes
Basic VHDL Constructs
VHDL examples
Resolved Signals
Pipelining
Parallel Designs
Previous Class Project: Convolution
Previous Final Project: LU Decomposition of a Matrix
Previous Final Project: Needleman Wunsch Algorithm for Sequence Alignment in Bioinformatic
Notes on FPGAs
Previous Pre/Post Test
Instructions on using ModelSim
source /afs/uncc.edu/coe/unix/opt/mgc/cshrc.en2002 vsim
Xilinx ISE Tutorial
Xilinx Virtex-5 FPGAs
Assignments
1.Example FIFO: fifo controller, fifo, testbench
Modify the above FIFO to handle network data packets, where each packet has 4 32-bit words :
Fall 2008 Midterm Solution BCD Counter FSM Delay
Mini-Project Solution 1 2 3 4 5 6
