Embedded Chip Multi-Processing
ECGR 6090/8090 – M01
Spring 2010
Lecture Timings 3:30pm – 4:45pm Monday, Wednesday
Room Woodward 140
Office Hours Wednesday 2:30 pm – 3:30 pm @ Woodward 235B
Instructor Dr. Ari Mukherjee
Course Objectives
Embedded systems are ubiquitous, and so are embedded processors with ever-increasing demands on high performance and low power operation. This has led to the emergence of increasingly powerful embedded chip multi-processors (ECMPs). The primary goal of this course is to introduce potential users of such ECMPs – students in widely varying disciplines and application areas – to the underlying hardware which is responsible for computation, power dissipation and meeting critical real-time constraints. Participants will gain a clearer understanding of the key architectural features of ECMPs which directly affect the performance of the embedded systems they work with, and gain insight about concepts and techniques necessary to design and select its hardware and software components. This is a very practical, results-oriented course that will provide knowledge and skills which can be applied immediately.
Course Description
Students will design and analyze industrial strength ECMPs using a cycle-accurate ECMP simulator CASPER (developed at UNCC in collaboration with Sun Microsystems), which targets the SPARCV9 instruction set. The simulator explores a large ECMP design space over a wide range of scalable architectural components. These components have been pre-characterized extensively to derive their delay, area and power libraries for the 45nm technology. As a result, any ECMP designed by the students as part of their final course project can be fabricated (although it is not part of this course). More importantly, students will be introduced to a suite of design automation algorithms and tools for analysis of the processor architectures in conjunction with scheduling techniques, and for studying their power-performance metrics. The course will begin with basic concepts in embedding processing and real-time operating systems, and gradually progress to complex issues in ECMPs. Three specific application domains – Intelligent Energy Systems, Mobile and Network Processing, and Wireless Sensor Networks – have been initially identified as potential application areas. The courses discusses in detail the architectural and power-performance trade-offs faced by hardware and software designers, along with power management techniques in ECMPs. The entire course is project and lab based.
Prerequisites None.
Textbook
None required. References will be provided in class.
Grading
Lab Assignments – 50 %, Final Project – 40%, Report – 10 %
Course Topics (Subject to change)
1. Embedded System Basics
Standards
Embedded Computer Systems Overview
2. Embedded Processors
Processor Architectures
Memory
Embedded Systems I/O
Buses
Commercial Processors (PowerPC, MIPS, ARM, IBM Kilocore, CBE)
3. Real Time Operating Systems Basics
Real Time Operating System (RTOS): Definitions and Issues
Task States and Task Scheduling
Survey of Task Schedulers
Introduction to Inter-task Communication and Synchronization
Message Passing from Task to Task
Semaphores and Shared Data
Liveness Issues: Deadlock, Lockout, Starvation
4. Real-time Scheduling
Partitioning of Software into Tasks
Rate Monotonic, Earliest Deadline First and other Scheduling Techniques
Low Power Real-Time Scheduling
5. ECMP Applications (list will be expanded)
Intelligent Energy Systems
Mobile and Network Processing
Wireless Sensor Networks
6. Designing ECMPs
Core Selection – Heterogeneous Multi-cores
Memory Organization – Hierarchy, Size, Associativity, Partition
Interconnect Design – Impact on Cache Coherence
7. Power Management
Hardware Power Management
Software Power Management
Operational Reliability – Hot-Spots, Power-Ground Noise
Lecture Notes
Will be added.
Resources
Generating Trace Files in SAM and Parsing Trace Files
CASPER – A Cycle-Accurate Heterogeneous ECMP Simulation Framework
Lab Assignments (Processor Designs will be evaluated on Simulator)
1. Compile Embedded Codes to Target Processor Instructions (Instruction Trace Files)
2. Study Memory Congestion in ECMPs – impact on Response Time and QoS – using a Memory Macro-Simulator
3. Design Optimum On-Chip Memory for a Target Embedded Application
4. Use CASPER (Full-Chip Cycle-Accurate ECMP Simulator) to –
vary Architectural Parameters and study Performance, Power, Energy and Area of the ECMP under simulation
5. Study Hardware controlled Power Management in ECMPs using CASPER
Course Project
Design an ECMP for a specific Application Domain
(Students have the option of picking applications in their research areas if available.
Otherwise, the instructor will provide applications for the final project.)
