ECGR 3181 Advanced Logic System Design

ECGR 3181 – Logic System Design II
SUMMER-I 2011  
Class Times: MTWTF 1pm – 2:30pm
Office Hours: MTWTF 12:30pm – 1pm
Final: 30%
Midterm: 30%
Project / Presentation: 40%  
Class Slides:
Combinational Logic
Sequential Logic
Race and Metastability in Sequential Circuits
Datapath Elements
Basic VHDL Constructs Pipelining   
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Counter
ButtonPress
TestBench
Notes on FPGAs
RTL Design
Programmable Processors   Final Project:
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IMAG0470-1.jpg Requirements for the Final Project Report: 1. Clear description of what you are designing (with pictures) [10%] 2. Picture of the FSM, along with word description of the different states and transitions [10%] 3. VHDL code implementing the FSM (describe the purpose of the different entities – if more than one) [20%] 4. VHDL Testbench of the Design-under-Test [10%] 5. Simulation waveform print-outs [10%] 6. State-Output Table (along with State Encodings) [5%] 7. K-Map based simplification of the Combinatorial Logic [10%] 8. Hardware Architecture of the FSM and Gate Diagram of the FSM implementation [10%] 9. PowerPoint Presentation [15%]
An example report
An example presentation   Important Dates: Midterm: June 9 Project Presentations: June 23, 24 Final: June 27