{"id":51,"date":"2016-08-31T18:06:29","date_gmt":"2016-08-31T22:06:29","guid":{"rendered":"https:\/\/coefs.charlotte.edu\/htabkhiv\/?page_id=51"},"modified":"2026-03-12T16:39:28","modified_gmt":"2026-03-12T20:39:28","slug":"publications","status":"publish","type":"page","link":"https:\/\/coefs.charlotte.edu\/htabkhiv\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"\n

Peer Reviewed Journals<\/strong><\/span><\/h2>\n\n\n\n
    \n
  1. S. Mohan, <\/span>O. Shoghli, A. Burde, and <\/span>H. Tabkhi<\/b>,<\/span>“A Low-Power Drone-Mountable Real-Time AI Framework for Road Asset Classification”, Transportation Research Record: Journal of the Transportation Research Board, In press, 2020.<\/span><\/span><\/li>\n\n\n\n
  2. J. Sanchez,<\/span> A. Sawant<\/span>, <\/span>C. Neff,<\/span> H. Tabkhi<\/b>,<\/span>\u00a0“AWARE-CNN: Automated Workflow for Application-aware Real-time Edge Acceleration of CNNs”,\u00a0<\/span> IEEE Internet of Things Journal,<\/span> May 2020, DOI: 10.1109\/JIOT.2020.2990215. <\/span>[Impact Factor: 9.5]<\/span><\/span><\/li>\n\n\n\n
  3. J. Zhang, <\/span>H. Tabkhi<\/b>, and G. Schirner,<\/span>\u00a0“Allocating One Common ACC-Rich Platform for Many Streaming Applications”,\u00a0<\/span>in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T-CAD), <\/span>Jan 2020<\/span>, DOI: 10.1109\/TCAD.2020.2967046.\u00a0<\/span><\/span><\/li>\n\n\n\n
  4. C. Neff, M. Mendieta, S. Mohan, M. Baharani, S. Rogers, and <\/span>H. Tabkhi<\/b>, “REVAMP2T: Real-time Edge Video Analytics for Multi-camera Privacy-aware Pedestrian Tracking”, IEEE Internet of Things Journal,<\/span> November 2019. <\/span>[Impact Factor: 9.5]<\/span><\/span><\/li>\n\n\n\n
  5. A. Purkayastha, S. Rogers, S. Shiddibhavi, and <\/span>H. Tabkhi<\/b>, “LLVM-Based OpenCL Sub-Kernel Parallelism for Automated Decoupled Memory Access on FPGAs”, Elsevier Journal of Parallel and Distributed Computing, <\/span>October 2019.\u00a0<\/span><\/span><\/li>\n\n\n\n
  6. M. Baharani, M. Biglarbegian, B. Parkhideh and <\/span>H. Tabkhi<\/b>, “Real-time Deep Learning at the Edge for Scalable Reliability Modeling of Si-MOSFET Power Electronics Converters”, <\/span>IEEE Internet of Things Journal<\/span><\/i>, vol. 6, no. 5, pp. 7375-7385, Oct. 2019.<\/span> [Impact Factor: 9.5]<\/span><\/span><\/li>\n\n\n\n
  7. S. Rogers, J, Slycord, R. V. Raheja, and <\/span>H. Tabkhi<\/b>, \u201cScalable LLVM-Based Accelerator Modeling in gem5\u201d, IEEE Computer Architecture Letters (CAL), <\/span>Vol. 18\u00a0,\u00a0<\/span>no. 1<\/span><\/a>\u00a0, Jan.-June, 2019.\u00a0<\/span><\/span><\/li>\n\n\n\n
  8. N. Teimouri, <\/span>H. Tabkhi<\/b>, and G. Schirner, “Alleviating Scalability Limitation of Accelerator-based Platforms”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T-CAD),<\/span>\u00a0Vol. 38\u00a0,\u00a0<\/span>no. 7<\/span><\/a>\u00a0, July 2019.<\/span><\/span><\/li>\n\n\n\n
  9. C. Zhang, <\/span>H. Tabkhi<\/b>, and G. Schirner, “Studying Inter-Warp Divergence Aware Execution on GPUs”, IEEE Computer Architecture Letters, vol.15, no. 2, pp.117-120 July-Dec. 2016.<\/span><\/span><\/li>\n\n\n\n
  10. H. Tabkhi<\/b>, R. Bushey, and G. Schirner, “Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications”, Springer Journal of Signal Processing and Systems, vol.85, no.1, pp.287\u2013306, Dec. 2016.<\/span><\/span><\/li>\n\n\n\n
  11. H. Tabkhi<\/b>, R. Bushey, and G. Schirner, “Conceptual Abstraction Levels (CALs) for Managing Design Complexity of Market-Oriented MPSoCs”, Elsevier Journal of Microprocessors and Microsystems, vol.39, no.8, pp. 704-719, Nov. 2015.<\/span><\/span><\/li>\n\n\n\n
  12. H. Tabkhi<\/b>, and G. Schirner, “A Joint SW\/HW Approach for Reducing Register File Vulnerability”, ACM Transactions on Architecture and Code Optimization (ACM TACO), vol.12, no.2, pp.1-28, May. 2015.<\/span><\/span><\/li>\n\n\n\n
  13. H. Tabkhi<\/b>, M. Sabbagh and G. Schirner, “A Power-Efficient Real-Time Solution for Adaptive Vision Algorithms”, IET Computers & Digital Techniques, vol.9, no.1, pp.16-26, Jan. 2015.<\/span><\/span><\/li>\n\n\n\n
  14. H. Tabkhi<\/b>, R. Bushey, and G. Schirner, “Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs”, IEEE Embedded Systems Letters, vol.6, no.4, pp.65-68, Dec. 2014.\u00a0<\/span><\/span><\/li>\n\n\n\n
  15. H. Tabkhi<\/b>, and G. Schirner, “Application-Guided Power Gating Reducing Register File Static Power”, IEEE Transactions on Very Large Scale Integration (TVLSI), vol.22, no.12, pp.2513-2526, Dec. 2014.<\/span><\/span><\/li>\n\n\n\n
  16. A. Patooghy, G. S Miremadi, and <\/span>H. Tabkhi<\/b>, “A Reliable and Power Efficient Flow-Control Method to Eliminate Crosstalk Faults in Network-on-Chips”, Microprocessors and Microsystems – Embedded Hardware Design, vol 35, no. 8, pp. 766-778, Nov. 2011.<\/span><\/span><\/li>\n<\/ol>\n\n\n\n

    Peer Reviewed Conference Papers <\/strong><\/span><\/h2>\n\n\n\n
      \n
    1. S. Rogers, J, Slycord, M. Baharani, and <\/span>H. Tabkhi<\/b>, \u201cgem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling\u201d, to appear in IEEE\/ACM International Symposium on Microarchitecture, Athens, Greece,\u00a0 October 17\u201321, 2020.<\/span><\/span><\/li>\n\n\n\n
    2. A. Purkayastha, J. Thiagarajan and <\/span>H. Tabkhi<\/b>, “Exploring the Scalability of OpenCL Coarse Grained Parallelism on Cloud FPGAs” <\/span>IEEE<\/b> International System-on-Chip Conference (<\/span>SOCC<\/b>), September 8-11, 2020.<\/span><\/span><\/li>\n\n\n\n
    3. A. Karimzadeh, S. Sabeti, <\/span>H. Tabkhi<\/b>, and O. Shoghli, \u201cCondition Prediction of Nearby Highway Assets\u00a0 Considering Their Interrelations: A Case Study\u201d, The International Association for Automation and Robotics in Construction, September 27-28, Kitakyshu, Japan, 2020.<\/span><\/span><\/li>\n\n\n\n
    4. A. Karimzadeh, S. Sabeti, A. Burde, <\/span>H. Tabkhi<\/b>, and O. Shoghli, \u201cSpatial-Temporal Deterioration of Multiple Highway Assets: A Correlational Study\u201d, Proceedings of ASCE Construction Research Congress (CRC), March 8-10, Tempe, Az. 2020.<\/span><\/span><\/li>\n\n\n\n
    5. \u00a0A. Karimzadeh, S. Sabeti, A. Burde, <\/span>H. Tabkhi<\/b>, and O. Shoghli, “Family Groups of Road Segments Considering Weather, Traffic, and Maintenance: A Clustering Approach”, Transportation Research Board Annual Meeting, Washington DC, Jan 2020.<\/span><\/span><\/li>\n\n\n\n
    6. J. Zhang, <\/span>H. Tabkhi<\/b>, and G. Schirner,<\/span>\u00a0<\/span>\u201cMitigating Application Diversity for Allocating a Unified ACC-Rich Platform\u201d, IEEE International Conference on Computer Design (ICCD), Abu Dhabi, UAE, Nov. 2019.\u00a0<\/span><\/span><\/li>\n\n\n\n
    7. A. Purkayastha, S. Raghavendran, J. Thiagarajan and <\/span>H. Tabkhi<\/b>, \u201cExploring the Efficiency of OpenCL Pipe for Hiding Memory Latency on Cloud FPGAs\u201d, IEEE High Performance Extreme Computing Conference (HPEC), Waltham, MA, Sep. 2019.<\/span><\/span><\/li>\n\n\n\n
    8. P. Kulkarni, S. Mohan, S. Rogers, and <\/span>H. Tabkhi<\/b>, \u201cKey-track: A lightweight scalable LSTM-based Pedestrian tracker for Surveillance systems\u201d, Springer International Conference on Image Analysis and Recognition, (ICIAR), Waterloo, Canada, August 2019.<\/span><\/span><\/li>\n\n\n\n
    9. M. Baharani, S. Mohan, and <\/span>H. Tabkhi<\/b>, \u201cReal-time Person Re-identification at the Edge: A Mixed Precision Approach\u201d, Springer International Conference on Image Analysis and Recognition (ICIAR), Waterloo, Canada, August 2019.<\/span><\/span><\/li>\n\n\n\n
    10. A. Willis, M. Mendieta, C. Neff, <\/span>H. Tabkhi<\/b>, “Measuring Compute-Reuse Opportunities for Video Processing Acceleration”, IEEE SoutheastCon, Huntsville, AL, April 2019.<\/span><\/span><\/li>\n\n\n\n
    11. M. Mendieta, C. Neff, D. Lingerfelt, C. Beam, A. George, S. Rogers, A. Ravindran, and <\/span>H. Tabkhi<\/b>,\u00a0 “A Novel Application\/Infrastructure Co-design Approach for Real-time Edge Video Analytics”, IEEE SoutheastCon, Huntsville, AL, April 2019.<\/span><\/span><\/li>\n\n\n\n
    12. J. Sanchez, R. Chamarthi, N. Soltani, A. Sawant, and <\/span>H. Tabkhi<\/b>, \u201cA Novel 1D-Convolution Accelerator for Low-Power Real-time CNN processing on the Edge\u201d IEEE High Performance Extreme Computing Conference (HPEC), Waltham, MA, Oct. 2018.<\/span><\/span><\/li>\n\n\n\n
    13. A. Purkayastha, S. Shiddibhavi and <\/span>H. Tabkhi<\/b>, \u201cTaxonomy of Spatial Parallelism on FPGAs for Massively Parallel Applications\u201d, 31st IEEE International System On Chip Conference, Arlington, VA, Sep. 2018.<\/span><\/span><\/li>\n\n\n\n
    14. M. Biglarbegian, M. Baharani, N. Kim, <\/span>H. Tabkhi<\/b> and B. Parkhideh, “Scalable Reliability Monitoring of GaN Power Converter through Recurrent Neural Networks,” IEEE Energy Conversion Congress and Exposition (ECCE), Portland, OR, 2018.<\/span><\/span><\/li>\n\n\n\n
    15. S. Rogers, <\/span>H. Tabkhi<\/b>, “Locality-Aware Memory Assignment and Tiling”, to be appeared in IEEE\/ACM Design Automation Conference (DAC), San Francisco, CA, USA, Jun 2018.<\/span><\/span><\/li>\n\n\n\n
    16. J. Sanchez, N. Soltani, P. Kulkarni, R. Chamarthi, and <\/span>H. Tabkhi<\/b>, “A Reconfigurable Streaming Processor for Real-Time Low-Power Execution of Convolutional Neural Networks at the Edge” to be appeared in International Conference on Edge Computing, Seattle, WA, USA, Jun 2018.<\/span> [<\/span>Best Paper Award<\/span>]<\/span><\/a><\/span><\/li>\n\n\n\n
    17. C. Bui, Nirali Patel, D. Patel, S. Rogers, A. Sawant, R. Manwatkar, and <\/span>H. Tabkhi<\/b>, “A Hardware\/Software Co-Design Approach for Real-Time Object Detection and Tracking on Embedded Devices” IEEE SoutheastCon, Tampa Bay Area, FL, April 2018.<\/span><\/span><\/li>\n\n\n\n
    18. J. Zhang, <\/span>H. Tabkhi<\/b> and G. Schirner, “DS-DSE: Domain-Specific Design Space Exploration for Streaming Applications”, to be appeared in IEEE\/ACM Design Automation and Tetst in Europe (DATE), Dresden, Germany, March 2018.<\/span><\/span><\/li>\n\n\n\n
    19. H. Tabkhi<\/b>, \u201cToward end-to-end object detection and tracking on the edge\u201d In Proceedings of the Second ACM\/IEEE Symposium on Edge Computing. ACM, San Jose, CA, USA, Oct. 2017.<\/span><\/span><\/li>\n\n\n\n
    20. A. Momeni, <\/span>H. Tabkhi<\/b>, G. Schirner and D. Kaeli, ” Hardware thread reordering to boost OpenCL throughput on FPGAs”, International Conference on Computer Design (ICCD), Phoenix, AZ, Oct. 2016.<\/span><\/span><\/li>\n\n\n\n
    21. A. Momeni, <\/span>H. Tabkhi<\/b>, G. Schirner and D. Kaeli, “OpenCL-based Optimizations for Acceleration of Object Tracking on FPGAs and GPUs”, International Workshop on Architectures and Systems for Real-time Mobile Vision Applications (ASR-MOV), in Conjunction with CGO’16, Barcelona, Spain, Mar. 2016.<\/span><\/span><\/li>\n\n\n\n
    22. H. Tabkhi<\/b>, M. Sabbagh and G. Schirner, “Guiding Power\/Quality Exploration for Communication-Intense Stream Processing” Great Lakes Symposium on VLSI (GLS-VLSI), Boston, MA, USA, May 2016.<\/span><\/span><\/li>\n\n\n\n
    23. N. Teimouri, <\/span>H. Tabkhi<\/b> and G. Schirner, “Improving Scalability of CMPs with Dense ACCs Coverage”, IEEE Design Automation and Test in Europe (DATE), Dresden, Germany, Mar. 2016.<\/span><\/span><\/li>\n\n\n\n
    24. M. Sabbagh, <\/span>H. Tabkhi<\/b> and G. Schirner, “Taming the Memory Demand Complexity of Adaptive Vision Algorithms”, IFIP International Embedded Systems Symposium (IESS), Foz do Iguacu, Brazil, Nov. 2015.<\/span><\/span><\/li>\n\n\n\n
    25. H. Tabkhi<\/b>, M. Sabbagh and G. Schirner, “An Efficient Architecture Solution for Low-Power Real-Time Background Subtraction”, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Toronto, Canada, Jul. 2015.<\/span><\/span><\/li>\n\n\n\n
    26. A. Momeni, <\/span>H. Tabkhi<\/b>, Y. Ukidave, G. Schirner and D. Kaeli, “Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA”, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Boston, MA, USA, Jun. 2015.<\/span><\/span><\/li>\n\n\n\n
    27. N. Teimouri, <\/span>H. Tabkhi<\/b>, and G. Schirner, “Revisiting Accelerator-Rich CMPs: Challenges and Solutions”, ACM\/EDAC\/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 2015.<\/span><\/span><\/li>\n\n\n\n
    28. Ch. Zhang, <\/span>H. Tabkhi<\/b> and G. Schirner, “A GPU-based Algorithm-specific Optimization for High-performance Background Subtraction”, International Conference on Parallel Processing (ICPP), Minneapolis, MN, USA, Sep. 2014.<\/span><\/span><\/li>\n\n\n\n
    29. H. Tabkhi<\/b>, R. Bushey and G. Schirner, “Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs”, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, Jun. 2014.<\/span><\/span><\/li>\n\n\n\n
    30. H. Tabkhi<\/b>, R. Bushey and G. Schirner, “Algorithm and Architecture Co-Design of Mixture of Gaussian (MoG) Background Subtraction for Embedded Vision”, IEEE Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), Monterey, CA, USA, Nov. 2013.<\/span><\/span><\/li>\n\n\n\n
    31. R. Bushey, <\/span>H. Tabkhi<\/b> and G. Schirner, \u201cFlexible Function-Level Acceleration of Embedded Vision Applications using the Pipelined Vision Processor\u201d, IEEE Asilomar Conference on Signals, Systems, and Computers (AsilomarSSC), Monterey, CA, USA, Nov. 2013.<\/span><\/span><\/li>\n\n\n\n
    32. R. Bushey, <\/span>H. Tabkhi<\/b> and G. Schirner, \u201cA Novel Quantitative ESL Based SOC Architecture Exploration Methodology\u201d, Analog Devices General Technical Conference (ADI GTC), Apr. 2013 (industry conference).<\/span><\/span><\/li>\n\n\n\n
    33. H. Tabkhi<\/b> and G. Schirner, \u201cAFReP: Application-guided Function-level Registerfile Power-gating for Embedded Processors\u201d, IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 2012.<\/span><\/span><\/li>\n\n\n\n
    34. H. Tabkhi<\/b> and G. Schirner, \u201cARRA: Application-guided Reliability-enhanced Registerfile Architecture for Embedded Processors\u201d, IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, CA, USA, Oct. 2012.<\/span><\/span><\/li>\n\n\n\n
    35. H. Tabkhi<\/b> and G. Schirner, \u201cApplication-Specific Power-Efficient Approach for Reducing Register File Vulnerability\u201d, IEEE Design Automation and Test in Europe (DATE), Dresden, Germany, Mar. 2012.<\/span><\/span><\/li>\n\n\n\n
    36. A. Patooghy, <\/span>H. Tabkhi<\/b> and G. S Miremadi, “An Efficient Method to Reliable Data Transmission in Network-on-Chips”, Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), Lille, France, Sep. 2010.<\/span><\/span><\/li>\n\n\n\n
    37. A. Patooghy, <\/span>H. Tabkhi<\/b> and G. S Miremadi, “RMAP: A Reliability-Aware Application Mapping for Network-on-Chips”, International Conference on Dependability (DEPEND), Venice\/Mestre, Italy, Jul. 2010.<\/span><\/span><\/li>\n\n\n\n
    38. H. Ghasemzadeh-Mohammadi, <\/span>H. Tabkhi<\/b>, G. S Miremadi and A. Ejlali, “A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic”, IEEE International Conference on Microelectronics (ICM), Sharjah, United Arab Emirates, Dec. 2008.<\/span><\/span><\/li>\n\n\n\n
    39. H. Tabkhi<\/b>, G. S Miremadi and A. Ejlali, “An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors”, IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (DFT), Cambridge, MA, USA, Oct. 2008.<\/span><\/span><\/li>\n<\/ol>\n\n\n\n

      Conference Poster Abstracts<\/strong><\/span><\/h2>\n\n\n\n
        \n
      1. J. Sanchez, N. Soltani, P. Kulkarni, and <\/span>H. Tabkhi<\/b>, “A Reconfigurable Domain-Specific Architecture for Real-Time CNN Processing at the Edge”, Late Breaking Results, Design Automation Conference (DAC), San Francisco, CA, June 2018.<\/span><\/span><\/li>\n\n\n\n
      2. A. Momeni, <\/span>H. Tabkhi<\/b>, G. Schirner and D. R. Kaeli, “Bridging Architecture and Programming for Throughput-Oriented Vision Processing”, International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey (CA), USA, Feb. 2015.<\/span><\/span><\/li>\n\n\n\n
      3. H. Tabkhi<\/b>, M. Sabbagh, and G. Schirner, \u201cA Power-efficient FPGA-based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution\u201d, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, MA, May 2014.<\/span><\/span><\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"

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