{"id":67,"date":"2012-04-02T10:04:25","date_gmt":"2012-04-02T14:04:25","guid":{"rendered":"https:\/\/coefs.charlotte.edu\/amukherj\/?page_id=67"},"modified":"2026-03-11T13:43:46","modified_gmt":"2026-03-11T17:43:46","slug":"publicationspatents","status":"publish","type":"page","link":"https:\/\/coefs.charlotte.edu\/amukherj\/publicationspatents\/","title":{"rendered":"Publications\/Patents"},"content":{"rendered":"\n

Journal Publications<\/strong><\/h2>\n\n\n\n
    \n
  1. A. Mukherjee and M. Marek-Sadowska, \u201cWave Steering to Integrate Logic and Physical Syntheses<\/em>\u201d, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, February 2003, pp.105-120.<\/li>\n\n\n\n
  2. A. Singh, A. Mukherjee, L. Macchiarulo and M. Marek-Sadowska, “PITIA : An FPGA for Throughput-Intensive Applications<\/em>“,\u00a0 IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11 ,\u00a0no. 3, \u00a0June 2003, pp.354\u2013363.<\/li>\n\n\n\n
  3. A. Mukherjee and M. Marek-Sadowska, “Clock and Power Gating with Timing Closure<\/em>“,\u00a0IEEE Design & Test Journal – Special Issue on Power-Supply Design and Analysis for ICs,\u00a0 May-June 2003, pp.32-39.<\/li>\n\n\n\n
  4. K. Regester, J. Byun, A. Mukherjee and A. Ravindran, \u201cImplementing bioinformatics algorithms on Nallatech-configurable multi-FPGA systems<\/em>\u201d, Xcell Journal., Second Quarter, 2005, pp.100-103.<\/li>\n\n\n\n
  5. F. Su, W. Hwang, A. Mukherjee and K. Chakrabarty, “Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips<\/em>“, Journal of Electronic Testing: Theory and Applications, 2006, pp.219-233.<\/li>\n\n\n\n
  6. K. Datta, A. Mukherjee and A. Ravindran, “Automated design flow for diode based nanofabrics<\/em>“, ACM Journal of Emerging Technologies in Computing Systems, vol, 2, no.3, July 2006, pp.219-241.<\/li>\n\n\n\n
  7. S. Mohan, A. Ravindran, D. Binkley and A. Mukherjee, “Power optimized design of CMOS Programmable Gain Amplifiers<\/em>\u201d, Journal of Low Power Electronics, Vol. 2, No:2, August 2006, pp.259-270.<\/li>\n\n\n\n
  8. R. Karanam, A. Ravindran, A. Mukherjee, C. Gibas, and A. Wilkinson, \u201cUsing FPGA-based Hybrid Computers for Bioinformatics Applications<\/em>\u201d, XCell Journal, Issue 58, Third Quarter, 2006, pp.80-83.<\/li>\n\n\n\n
  9. D. Davids, S. Datta, A. Mukherjee, B. Joshi and A. Ravindran, “Multiple Fault Diagnosis in Digital Microfluidic Biochips<\/em>“, ACM Journal on Emerging Technologies in Computing Systems, vol. 2, no. 4,\u00a0October 2006, pp.262-276.<\/li>\n\n\n\n
  10. S. Tucker, A. Ravindran, C. Wichman, and A. Mukherjee, “Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters<\/em>“, Journal of Low Power Electronics, Vol. 3., April 2007, pp.1-10.<\/li>\n<\/ol>\n\n\n\n

    Conference Publications<\/strong><\/h2>\n\n\n\n
      \n
    1. A. Mukherjee, M. Marek-Sadowska and S. I. Long, “Wave Pipelining YADDs : A Feasibility Study<\/em>“, Proceedings of IEEE Custom Integrated Circuits Conference , May 1999, pp.559-562.<\/li>\n\n\n\n
    2. A. Mukherjee, R. Sudhakar, M. Marek-Sadowska and S. I. Long, “Wave Steering in YADDs : A Novel Non-iterative Synthesis and Layout Technique<\/em>“, Proceedings of IEEE Design Automation Conference , June 1999, pp.466-471.<\/li>\n\n\n\n
    3. A. Singh, L. Macchiarulo, A. Mukherjee and M. Marek-Sadowska, “A Novel High Throughput FPGA Architecture<\/em>“, Proceedings of ACM International Symposium on FPGAs, February 2000, pp.22-29.<\/li>\n\n\n\n
    4. A. Singh, A. Mukherjee and M. Marek-Sadowska, “Interconnect Pipelining in a Throughput Intensive FPGA Architecture<\/em>“, Proceedings of ACM International Symposium on FPGAs, February 2001, pp.153-160.<\/li>\n\n\n\n
    5. G. Parthasarathy, M. Marek-Sadowska, A. Mukherjee and A. Singh, “Interconnect Complexity-Aware FPGA Placement using Rent’s rule<\/em>“, Proceedings of IEEE System Level Interconnect Prediction, March 2001.<\/li>\n\n\n\n
    6. A. Singh, A. Mukherjee and M. Marek-Sadowska, “Latency and Latch Count Minimization in Wave Steered Circuits<\/em>“, Proceedings of IEEE Design Automation Conference, June 2001, pp.383-388.<\/li>\n\n\n\n
    7. N. Funabiki, A. Singh, A. Mukherjee and M. Marek-Sadowska, “A Global Routing Technique for Wave Steered Circuits<\/em>“, Proceedings of IEEE EuroMICRO Digital System Design, August 2001, pp.430-436.<\/li>\n\n\n\n
    8. A. Mukherjee, K. Wang, L. -H. Chen and M. Marek-Sadowska, “Sizing Power\/Ground Meshes for Clocking and Computing Circuit Components<\/em>“, Proceedings of IEEE Design, Automation and Test in Europe Conference, March 2002, pp.176-183.<\/li>\n\n\n\n
    9. A. Mukherjee, K. R. Dusety and R. Sankaranarayan, “A practical CAD technique for reducing power\/ground noise in DSM circuits<\/em>“,\u00a0Proceedings of IEEE\/ACM Great Lakes Symposium on VLSI, April 2003, pp.96-99.<\/li>\n\n\n\n
    10. A. Mukherjee, R. Sankaranarayan and K. R. Dusety, “Layout-aware gate-sizing and buffer insertion for low-power low-noise DSM circuits<\/em>“, Proceedings of IEEE ASIC-SOC Conference, September 2003.<\/li>\n\n\n\n
    11. A. Mukherjee, “On the reduction of Simultaneous Switching in SoCs<\/em>“, Proceedings of IEEE International Symposium on VLSI, February, 2004.<\/li>\n\n\n\n
    12. A. Mukherjee and R. Sankaranarayan, “Retiming and Clock Scheduling to minimize Simultaneous Switching<\/em>“, Proceedings of IEEE International System-on-Chip Conference, September, 2004.<\/li>\n\n\n\n
    13. A. Mukherjee, “Reducing Crosstalk Noise in High Speed FPGAs<\/em>“, Proceedings of IEEE International System-on-Chip Conference, September, 2004.<\/li>\n\n\n\n
    14. J. Bolano, J. Johnson, A. Wood, A. Mukherjee, H. Hilger and A. Ravindran, \u201cReal time wireless remote monitoring of methane flux in landfills<\/em>\u201d, Proceedings of International Conference on Energy, Enviroment and Disasters, July 2005.\u00a0<\/li>\n\n\n\n
    15. F. Su, W. Hwang, A. Mukherjee and K. Chakrabarty, “Defect-Oriented Testing and Diagnosis of Digital Microfluidics-Based Biochips<\/em>“, Proceedings of IEEE International Test Conference, 2005.<\/li>\n\n\n\n
    16. K. Datta, A. Mukherjee and A. Ravindran, “Routing for Reliability in Molecular Diode-based Nanofabrics<\/em>“, Proceedings of the 8th Military and Aerospace Programmable Logic Device (MAPLD) International Conference, September 2005.<\/li>\n\n\n\n
    17. A. Mukherjee, “The Biochip Journey from the Lab to the Field – A System Designer’s Perspective<\/em>“, Proceedings of the IEEE Design Automation and Test in Europe (DATE) conference – Special Workshop on Biochips, March 2006.<\/li>\n\n\n\n
    18. J. Bolano, O. Eruotor, Y. Nerie, K. Datta, A. Mukherjee and A. Ravindran, \u201cThe Wireless Sensor Tissue: A Network of Wireless Sensor Nodes using Cellular Mechanisms for Autonomous Distributed Fault Tolerance<\/em>\u201d, Proceedings of IEEE 15th<\/sup>North Atlantic Test Workshop, May 2006.<\/li>\n\n\n\n
    19. K. Datta, R. Karanam, J-H. Byun, A. Mukherjee, B. Joshi and A. Ravindran, \u201cVIVO: A Biology-inspired Self-Repairable Distributed Fault Tolerant Design Methodology with Efficient Redundancy Insertion Technique<\/em>\u201d,Proceedings of IEEE 15th<\/sup>North Atlantic Test Workshop, May 2006.<\/li>\n\n\n\n
    20. J. Byun, R. Karanam, A. Ravindran, A. Mukherjee and B. Joshi, “Fault Tolerant Techniques for I\/O Bound High Performance Systolic Arrays on SRAM FPGAs<\/em>“, Proceedings of the 9th Military and Aerospace Programmable Logic Device (MAPLD) International Conference, September 2006.<\/li>\n\n\n\n
    21. R. K. Karanam, A. Ravindran and A. Mukherjee, ” A Stream Multiprocessor System-On-Chip Architecture for FPGA Acceleration of Bioinformatics Applications<\/em>“, Submitted to the Special Session on Reconfigurable Computing for Biological Data Analysis, IEEE 7th<\/sup> International Symposium on BioInformatics and BioEngineering 2007.<\/li>\n<\/ol>\n\n\n\n

       <\/p>\n\n\n\n

          Book Chapter<\/strong><\/span><\/h2>\n\n\n\n

          B. Joshi, A. Mukherjee and A. Ravindran, \u201cEmerging Digital Microfluidic Biochips\u201d, CMOS circuits for Emerging Technologies<\/em><\/strong>, Chapter 4.3, Publisher Artech House, Editor Kris Iniewski, 2007.<\/p>\n\n\n\n

          Book<\/strong><\/span> <\/strong><\/p>\n\n\n\n

          S. Mukherjee and A. Mukherjee, Entrepreneurship Development and Business Communication<\/em><\/strong>, Publisher B.B. Kundu Grandsons, India, 1st<\/sup> edition July 2003, 2nd<\/sup> edition July 2004.<\/p>\n\n\n\n

      US Patent<\/strong><\/span><\/h2>\n\n\n\n

      Title : Methodology for Scheduling, Partitioning and Mapping Computational Tasks onto Scalable, High Performance, Hybrid FPGA Networks<\/p>\n\n\n\n

      Inventors : Arindam Mukherjee and Arun Ravindran<\/p>\n\n\n\n

      Filing Date : June 15, 2005.<\/p>\n\n\n\n

      Provisional Patent<\/strong><\/span><\/h2>\n\n\n\n

      Title : FPGA based Hardware Accelerators for Bioinformatics<\/p>\n\n\n\n

      Inventors : Arindam Mukherjee and Arun Ravindran<\/p>\n\n\n\n

      Filing Date : June 15, 2004.<\/p>\n\n\n\n

      Report of Invention<\/strong><\/span><\/h2>\n\n\n\n

      Title : Fabrication of a nanosensor DNA microarray chip<\/p>\n\n\n\n

      Inventors : Mahnaz El-Kouedi, Aja Andreu, Kayvan Najarian, Robert Splinter, Arindam Mukherjee, Arun Ravindran,and Mohamed Ali Hasan.<\/p>\n\n\n\n

      Filing Date : July 14, 2004.<\/p>\n","protected":false},"excerpt":{"rendered":"

      Journal Publications Conference Publications       Book Chapter     B. Joshi, A. Mukherjee and A. Ravindran, \u201cEmerging Digital Microfluidic Biochips\u201d, CMOS circuits for Emerging Technologies, Chapter 4.3, Publisher Artech House, Editor Kris Iniewski, 2007.     Book     S. Mukherjee and … Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":168,"featured_media":0,"parent":0,"menu_order":3,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-67","page","type-page","status-publish","hentry"],"jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/67","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/users\/168"}],"replies":[{"embeddable":true,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/comments?post=67"}],"version-history":[{"count":5,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/67\/revisions"}],"predecessor-version":[{"id":704,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/67\/revisions\/704"}],"wp:attachment":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/media?parent=67"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}