{"id":34,"date":"2012-04-28T09:59:14","date_gmt":"2012-04-28T13:59:14","guid":{"rendered":"https:\/\/coefs.charlotte.edu\/amukherj\/?page_id=34"},"modified":"2026-03-11T13:53:46","modified_gmt":"2026-03-11T17:53:46","slug":"ecgr-4146ecgr5146-hardware-acceleration-using-fpgas","status":"publish","type":"page","link":"https:\/\/coefs.charlotte.edu\/amukherj\/teaching\/ecgr-4146ecgr5146-hardware-acceleration-using-fpgas\/","title":{"rendered":"ECGR 4146\/ECGR5146 Hardware Acceleration using FPGAs"},"content":{"rendered":"\n

Advanced System Design using HDLs <\/span><\/strong><\/span><\/h1>\n\n\n\n

Catalog Listing “Introduction to VHDL”(ECGR 4146\/5146 )<\/span><\/strong><\/h1>\n\n\n\n

Spring 2011<\/span><\/strong><\/h1>\n\n\n\n

\u00a0\u00a0\"waterfall\"<\/h2>\n\n\n\n

A Design Flow is similar to a Cascading Waterfall<\/span><\/strong><\/h2>\n\n\n\n

Lecture Timings<\/strong> <\/em><\/span>12:30pm – 1:45pm Tuesday, Thursday         Room: Woodward 140<\/span><\/span><\/h2>\n\n\n\n

TA for class : None<\/span><\/h2>\n\n\n\n

TA office : None<\/span><\/h2>\n\n\n\n

TA office hours : None<\/span><\/h2>\n\n\n\n

Instructor office hours : Tuesdays, Thursdays 11:30pm – 12:30 pm @ Woodward 235B<\/span><\/h2>\n\n\n\n

Instructor<\/strong><\/span> Dr. Arindam Mukherjee<\/strong><\/span><\/span><\/h2>\n\n\n\n

Course Description<\/span><\/strong><\/span><\/h2>\n\n\n\n

This course is designed for junior\/senior undergraduate students with a background in digital logic design and VHDL. The class meets twice a week with alternating lectures and laboratories. The lectures and laboratory sessions seeks to impart students the ability for FPGA based reconfigurable hardware implementation of computationally intensive algorithms from diverse areas such as bioinformatics, scientific computing and image processing. No background knowledge of these topics is required. Students are required to complete a design project involving implementation of a real world computational application on FPGAs. CAD tools including Xilinx ISE design flow and Modelsim are used extensively throughout the course.<\/span><\/p>\n\n\n\n

Course Objectives<\/span><\/strong><\/span><\/h2>\n\n\n\n

Ability to describe digital logic in VHDL.<\/span><\/h2>\n\n\n\n

Familiarity with FPGA design flow including interfacing issues.<\/span><\/h2>\n\n\n\n

Exposure to computing algorithms from diverse application areas.<\/span><\/h2>\n\n\n\n

Ability to map computationally intensive algorithms to FPGAs.<\/span><\/h2>\n\n\n\n

Successful project execution and presentation of results working in a team.<\/span><\/h2>\n\n\n\n

Prerequisites<\/span><\/strong><\/span><\/h2>\n\n\n\n

 ECGR 3181 Advanced Digital Logic Systems.<\/span><\/h2>\n\n\n\n

Textbook  <\/strong><\/span>   <\/span><\/h2>\n\n\n\n

 Peter J. Ashenden, THE DESIGNER’S GUIDE TO VHDL, Third Edition, Elsevier Publishers, 2008.<\/span>
\nGrading<\/strong><\/span><\/strong><\/span>
\nMidterm ? 20%, Class Projects – 20%, Final ? 30%, Final Project and Presentation ? 30%<\/span>
\nCourse Topics (Subject to change)<\/strong><\/strong><\/span> <\/p>\n\n\n\n

    \n
  1. Review ofFiniteStateMachines<\/span><\/li>\n\n\n\n
  2. Overview of VHDL ? Structure and Syntax<\/span><\/li>\n\n\n\n
  3. Overview of VHDL ? Modeling<\/span><\/li>\n\n\n\n
  4. Overview of VHDL – Synthesis<\/span><\/li>\n\n\n\n
  5. FPGA Design Flow<\/span><\/li>\n\n\n\n
  6. Interfacing FPGA based hardware accelerators to computers<\/span><\/li>\n\n\n\n
  7. Design Case Studies<\/span><\/li>\n\n\n\n
  8. Projects<\/span><\/li>\n<\/ol>\n\n\n\n

     <\/span>
    \nLecture Notes<\/strong><\/span>
    \n                              Basic VHDL Constructs<\/a> <\/span>
    \n                                  VHDL examples<\/a><\/span>
    \n    Resolved Signals<\/a><\/span>
    \n    Pipelining<\/a><\/span>
    \n    Parallel Designs<\/a><\/span>
    \nPrevious     Class Project: Convolution<\/a><\/span>
    \nPrevious     Final Project: LU Decomposition of a Matrix<\/a><\/span>
    \nPrevious     Final Project: Needleman Wunsch Algorithm for Sequence Alignment in Bioinformatic<\/a><\/span>
    \n    Notes on FPGAs<\/a><\/span>
    \n                                <\/span>
    \n                                Previous     Pre\/Post Test<\/a><\/strong><\/span>
    \n <\/span>
    \nInstructions on using ModelSim<\/strong><\/span>
    \nsource \/afs\/uncc.edu\/coe\/unix\/opt\/mgc\/cshrc.en2002 vsim<\/strong><\/span>
    \n                                    Xilinx ISE Tutorial<\/a><\/strong><\/span>                                
    \n    Xilinx Virtex-5 FPGAs<\/a>
    \n                                Assignments<\/strong><\/span><\/span>
    \n1.Example FIFO:     fifo controller<\/a>, fifo<\/a>, testbench<\/a><\/span>
    \nModify the above FIFO to handle network data packets, where each packet has 4 32-bit words : <\/strong><\/span>
    \n<\/strong>
    \nFall 2008 Midterm Solution        BCD Counter<\/a>    FSM<\/a>    Delay<\/a><\/strong><\/span>
    \nMini-Project Solution        1<\/a>    2<\/a>    3<\/a>    4<\/a>    5<\/a>    6<\/a><\/strong><\/span>
    \n<\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"

    Advanced System Design using HDLs  Catalog Listing “Introduction to VHDL”(ECGR 4146\/5146 ) Spring 2011 \u00a0\u00a0 A Design Flow is similar to a Cascading Waterfall Lecture Timings 12:30pm – 1:45pm Tuesday, Thursday         Room: Woodward 140 TA for class : None TA office … Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":168,"featured_media":0,"parent":15,"menu_order":3,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-34","page","type-page","status-publish","hentry"],"jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/34","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/users\/168"}],"replies":[{"embeddable":true,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/comments?post=34"}],"version-history":[{"count":5,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/34\/revisions"}],"predecessor-version":[{"id":713,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/34\/revisions\/713"}],"up":[{"embeddable":true,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/15"}],"wp:attachment":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/media?parent=34"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}