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Lecture<\/strong> <\/p>\n\n\n\n Instructor<\/strong> <\/strong> <\/strong> VLSI System Design ECGR 4433\/5133 Spring 2011 LectureTimings 5 pm \u2013 7:30 pm Monday Room Woodward 140Office Hours Monday 3:30 pm \u2013 5 pm @ Woodward 235B InstructorDr. Arindam MukherjeeCourse Description This course is designed for students … Continue reading
<\/strong>
Timings<\/strong>
<\/em><\/strong>
<\/strong>
5 pm \u2013 7:30 pm Monday <\/strong>
<\/strong>
Room<\/strong>
Woodward 140<\/strong>
<\/strong>
Office Hours<\/strong>
<\/strong>
Monday 3:30 pm \u2013 5 pm @ Woodward 235B<\/strong><\/p>\n\n\n\n
Dr. Arindam Mukherjee<\/strong>
Course Description<\/strong>
<\/strong> This course is designed for students with a preliminary background in logic system design. The course introduces the techniques used in the synthesis, physical design and fabrication of VLSI chips, specifically targeting Embedded Chip MultiProcessors (CMPs). The course begins with the fundamental elements of transistor based switching, different logic families, and gradually builds up processor components and cores, ultimately leading up the design of an Embedded CMP. Fundamental processor architectural concepts are introduced, with focus on Embedded low-power real-time constrained CMPs. In addition, students will be introduced to leading Industrial CAD tools used today for VLSI and ULSI chip design.
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Course Objectives<\/strong>
<\/strong> The primary goal of this course is to introduce students to VLSI System-on-a-Chip Design, and to give the participants the concepts and techniques necessary to design and verfiy a low-power real-time constrained Embedded Chip MultiProcessor in ultra-Deep-Sub-Micron technology. This is a very practical, results-oriented course that will provide knowledge and skills that can be applied immediately.<\/p>\n\n\n\n
Prerequisites<\/strong>
<\/strong>Logic System Design II (ECGR 3181)<\/p>\n\n\n\n
\nPrerequisites<\/strong>
\n<\/strong> Logic System Design II (ECGR 3181)
\n<\/strong>
\nTextbook <\/strong>
\n<\/strong> Modern VLSI Design: IP-Based Design (4th Edition) by Wayne Wolf (Hardcover – Dec 31, 2008)
\nGrading<\/strong>
\n<\/strong> Midterm – 30%, Final – 30%, Project ? 40%
\nLecture Notes<\/strong>
\nSet1<\/a>
\nSet2<\/a>
\nSet3<\/a>
\nSet4<\/a>
\nSet5<\/a>
\nSet6<\/a>
\nSet7<\/a>
\nSet8<\/a>
\nSet9<\/a>
\nSet10<\/a>
\nSet11<\/a>
\nSet13<\/a>
\nSet14<\/a>
\nResources<\/strong>
\nSpice Links<\/a>,
\nCadence Spice Manual<\/a><\/strong>
\nSpice Examples<\/a> Example: FPU of SUN UltraSPARC T1:
\nFPU.vhd<\/strong><\/a>
\nfull adder<\/strong><\/a>
\nSynopsys Design Vision Simplified Manual<\/a>
\nDesign Vision More Detailed Manual<\/a>
\nDesign Vision – Timing Analysis<\/a>
\nFinal Design Vision Manual<\/a><\/strong>
\nDesign Vision Database in 45nm Technology<\/strong><\/a> [ .db attachment]
\nCadence Encounter Simplified Manual<\/a>
\nFinal Encounter Manual<\/a><\/strong>
\nNeeded files for Encounter<\/a><\/strong>
\nRC Output File Formats<\/a><\/strong>
\nExample RC Files<\/strong> <\/a>
\nClass Demos<\/strong>
\n<\/strong>
\n inverter.doc<\/a>
\n Course Project<\/strong>
\n <\/strong>
\nLocation of SPICE netlists<\/a>
\nContents of your final report<\/a>
\nDesign Rules<\/a><\/span><\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"