{"id":17,"date":"2012-04-28T10:00:15","date_gmt":"2012-04-28T14:00:15","guid":{"rendered":"https:\/\/coefs.charlotte.edu\/amukherj\/?page_id=17"},"modified":"2026-03-11T13:47:17","modified_gmt":"2026-03-11T17:47:17","slug":"ecgr-3181-advanced-logic-system-design","status":"publish","type":"page","link":"https:\/\/coefs.charlotte.edu\/amukherj\/teaching\/ecgr-3181-advanced-logic-system-design\/","title":{"rendered":"ECGR 3181 Advanced Logic System Design"},"content":{"rendered":"\n

ECGR 3181 – Logic System Design II<\/strong>
SUMMER-I 2011<\/strong> \u00a0
Class Times: MTWTF 1pm – 2:30pm<\/strong>
Office Hours: MTWTF 12:30pm – 1pm<\/strong>
Final: 30%<\/strong>
Midterm: 30%<\/strong>
Project \/ Presentation: 40%<\/strong> \u00a0
Class Slides:<\/strong>
Combinational Logic<\/a>
Sequential Logic<\/a>
Race and Metastability in Sequential Circuits<\/a>
Datapath Elements<\/a>
Basic VHDL Constructs<\/a> Pipelining\u00a0\u00a0\u00a0
IMAG0471-2.jpg<\/a>
Counter<\/a>
ButtonPress<\/a>
TestBench<\/a>
Notes on FPGAs<\/a>
RTL Design<\/a>
Programmable Processors<\/a> \u00a0 Final Project:
IMAG0469-1.jpg<\/a>\u00a0\u00a0\u00a0
IMAG0470-1.jpg<\/a> Requirements for the Final Project Report: 1. Clear description of what you are designing (with pictures) [10%] 2. Picture of the FSM, along with word description of the different states and transitions [10%] 3. VHDL code implementing the FSM (describe the purpose of the different entities – if more than one) [20%] 4. VHDL Testbench of the Design-under-Test [10%] 5. Simulation waveform print-outs [10%] 6. State-Output Table (along with State Encodings) [5%] 7. K-Map based simplification of the Combinatorial Logic [10%] 8. Hardware Architecture of the FSM and Gate Diagram of the FSM implementation [10%] 9. PowerPoint Presentation [15%]
An example report<\/a>
An example presentation<\/a> \u00a0 Important Dates: Midterm: June 9 Project Presentations: June 23, 24 Final: June 27<\/p>\n","protected":false},"excerpt":{"rendered":"

ECGR 3181 – Logic System Design II SUMMER-I 2011 \u00a0 Class Times: MTWTF 1pm – 2:30pm Office Hours: MTWTF 12:30pm – 1pm Final: 30% Midterm: 30% Project \/ Presentation: 40% \u00a0 Class Slides: Combinational Logic Sequential Logic Race and Metastability … Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":168,"featured_media":0,"parent":15,"menu_order":1,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-17","page","type-page","status-publish","hentry"],"jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/17","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/users\/168"}],"replies":[{"embeddable":true,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/comments?post=17"}],"version-history":[{"count":5,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/17\/revisions"}],"predecessor-version":[{"id":708,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/17\/revisions\/708"}],"up":[{"embeddable":true,"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/pages\/15"}],"wp:attachment":[{"href":"https:\/\/coefs.charlotte.edu\/amukherj\/wp-json\/wp\/v2\/media?parent=17"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}